Commits
Shardar Shariff Md committed b9c2470fb15
serial: tegra: flush the RX fifo on frame error FIFO reset/flush code implemented now does not follow programming guidelines. RTS line has to be turned off while flushing FIFOs to avoid new transfers. Also check LSR bits UART_LSR_TEMT and UART_LSR_DR to confirm FIFOs are flushed. Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Link: https://lore.kernel.org/r/1567572187-29820-4-git-send-email-kyarlagadda@nvidia.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>