Commits
Dirk Behme committed bc3d8ede3a1
ARM: imx: Do L2 errata only if the L2 cache isn't enabled All the generic L2 cache handling code is encapsulated by a check if the L2 cache is enabled. If it's enabled already, the code is skipped. The write to the L2-Cache controller from non-secure world causes an imprecise external abort. This is needed in scenarios where one of the cores runs an other OS, e.g. an RTOS. For the i.MX6 specific L2 cache handling we missed this check. Add it. Signed-off-by: Marcel Grosshans <MarcelViktor.Grosshans@de.bosch.com> Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>