Commits
Jiaxin Yu committed ccb1fa21ef5
ASoC: mediatek: mt6358: add delay after dmic clock on Most dmics produce a high level when they receive clock. The difference between power-on and memory record time is about 10ms, but the dmic needs 50ms to output normal data. This commit add 100ms delay after SoC output clock so that we can cut off the pop noise at the beginning. Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> Link: https://lore.kernel.org/r/1564980997-11359-1-git-send-email-jiaxin.yu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>