Commits
Zhong Kaihua committed d33fb1b9f0f
clk: hi3660: fix incorrect uart3 clock freqency UART3 clock rate is doubled in previous commit. This error is not detected until recently a mezzanine board which makes real use of uart3 port (through LS connector of 96boards) was setup and tested on hi3660-hikey960 board. This patch changes clock source rate of clk_factor_uart3 to 100000000. Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com> Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>