Commits
Kefeng Wang committed dbb58d0f792
arm64: dts: hip05: Add L2 cache topology The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus share one L2 cache, add them to the dtsi file so that the cache hierarchy can be probed. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>