Commits
Merge tag 'sunxi-clk-for-4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull allwinner clock changes from Maxime Ripard: Our usual set of changes for the Allwinner SoCs clock support. The most notable changes are: - A bunch of changes and fixes to support the A64 display engine - Some fixes to support the A83t display engine * tag 'sunxi-clk-for-4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro clk: sunxi-ng: a64: Add max. rate constraint to video PLLs clk: sunxi-ng: a64: Add minimal rate for video PLLs clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs clk: sunxi-ng: nkmp: Add constraint for maximum rate clk: sunxi-ng: r40: Add max. rate constraint to video PLLs clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video clk: sunxi-ng: Add maximum rate constraint to NM PLLs clk: sunxi-ng: h6: fix PWM gate/reset offset clk: sunxi-ng: h6: fix bus clocks' divider position
