Commits
Eugeniy Paltsev committed f6a09bace0b
ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk Add core pll node (core_clk) to manage cpu frequency. core_clk represents pll itself. input_clk represents clock signal source (basically xtal) which comes to pll input. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>