Commits
Geert Uytterhoeven committed fdd0dbd8a28
ARM: dts: r8a7793: Add L2 cache-controller node Add a device node for the L2 cache, and link the CPU node to it. The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as 64 KiB x 16 ways). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>