Commits
Gary R Hook committed ff18c4e598d
iommu/amd: Set the device table entry PPR bit for IOMMU V2 devices The AMD IOMMU specification Rev 3.00 (December 2016) introduces a new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register offset 0030h (IOMMU Extended Feature Register). When EPHSup=1, the IOMMU hardware requires the PPR bit of the device table entry (DTE) to be set in order to support PPR for a particular endpoint device. Please see https://support.amd.com/TechDocs/48882_IOMMU.pdf for this revision of the AMD IOMMU specification. Signed-off-by: Gary R Hook <gary.hook@amd.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>