linux-phytec-ti

PCI: mvebu: Drop writes to bridge Secondary Status register

There are no writable bits in the secondary status register, only RO and
RW1C (write-1-to-clear) bits.  The driver never sets any of the RW1C bits,
so the status register should always be 0, just remove the set from the
write path.

Someday the RW1C bits should be copied/cleared directly from registers in
the HW.

[bhelgaas: changelog tweaks]
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>