Commits
Zhuoyu Zhang committed bfa709bc823
cpufreq: powerpc: add cpufreq transition latency for FSL e500mc SoCs According to the data provided by HW Team, at least 12 internal platform clock cycles are required to stabilize a DFS clock switch on FSL e500mc Socs. This patch replaces the CPUFREQ_ETERNAL with appropriate HW clock transition latency to make DFS governors work normally on Freescale e500mc boards. Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>