uboot-imx

usb: dwc3: gadget: Set all ctrl fields of Transfer Control Blocks (TRB) to be LST

It turned out that current dwc3 gadget code is preparing multiple TRBs
for a transfer. Unfortunately, when multiple requests are in the same
queue, only for the last one the LST (last) ctrl bit is set.

Due to that dwc3 HW executes all TRBs up till the one marked as last.
Unfortunately, UMS requires call of ->complete callback after any send TRB.
This is the reason for "hangs" in executing UMS.

This code simplifies this situation and set each TRB's ctrl field bit to be
last (LST bit).

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>