Commits
Bryan Brinsko committed 97840b5d1fe
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>