Commits
Ye Li committed a6b88e53745
MLK-14689 mx7ulp: Workaround APLL PFD2 to 345.6Mhz The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider set to 1. This frequecy is out of ULP A0 spec. The MAX rate for GPU is 350Mhz. So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28) to workaround the problem. The correct fix should let GPU handle the clock rate in kernel. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit e931d534fd68e0e639082766de17a20e705fd908) (cherry picked from commit e72f766c98a3df9b620feb51484e33c7d50bed3c) (cherry picked from commit da29f331eded32b5de637ef2c4664b43ab184cee)