Commits
Rongjun Ying committed 00954c1bdb7
ARM: dts: sirf: add pin group for USP0 with only RX or TX frame sync for atlas6 add pin groups for USP0 only holding one of TX and RX frame sync. this patch matches with the change in drivers/pinctrl/sirf. commit 73f68c01f46 did this for prima2, but missed prima2. this patch fixes the problem. Signed-off-by: Rongjun Ying <rongjun.ying@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>