linux-phytec-fsl

Revert "drm/radeon: use variable UVD clocks"

This caused reduced performance for some users with advanced post
processing enabled.  We need a better method to pick the
UVD state based on the amount of post processing required or tune
the advanced post processing to fit within the lower power state
envelope.

This reverts commit 14a9579ddbf15dd1992a9481a4ec80b0b91656d5.
Cc: "3.15" <stable@vger.kernel.org>