Commits
Andy Duan committed 080b50a0ead
MLK-13910: ARM: imx7d: clk: correct enet clock CCGR register offset Correct enet clock CCGR register offset. CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 enet2 bus clocks) CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK IMX7D_ENET_PHY_REF_ROOT_DIV supply clock for PHY, no gate after the clock, its parent clcok root has gate. IMX7D_ENET1_REF_ROOT_DIV/IMX7D_ENET2_REF_ROOT_DIV supply clocks for enet IPG_CLK_RMII, no gate after the clock, its parent clock root has gate. IMX7D_PLL_ENET_MAIN_125M_CLK (anatop pll) supply clock for enet RGMII tx_clk. Update copyright information. Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>