linux-phytec-fsl

drm/fsl-dcu: use bus_flags for pixel clock polarity

The drivers current default configuration drives the pixel data
on rising edge of the pixel clock. However, most display sample
data on rising edge... This leads to color shift artefacts visible
especially at edges.

This patch changes the relevant defines to be useful and actually
set the bits, and changes pixel clock polarity to drive the pixel
data on falling edge by default. The patch also adds an explicit
pixel clock polarity flag to the display introduced with the driver
(NEC WQVGA "nec,nl4827hc19-05b") using the new bus_flags field to
retain the initial behavior.

Signed-off-by: Stefan Agner <stefan@agner.ch>