linux-phytec-fsl

MLK-14851: ASoC: wm8962: fix clock issue for S20_3LE

There is error log "wm8962 3-001a: Unsupported BCLK ratio 6"
When the bitstream's format is S20_3LE.
The reason is that the pll output is samplerate*256, which
can't divide to clock samplerate*20*2. So in this patch change
the pll output to samplerate*384, and use the physical_width
for S20_3LE to calculate the bclk.

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>