Commits
Alexander Shiyan committed 402e4a4c532
ARM: i.MX1 clk: Add missing clocks This patch adds missing clocks for mpll_gate, spll_gate, uart3_gate, ssi2_gate and brom_gate. As an additional this fixes incorrect bit position for dma_gate clock. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>