linux-phytec-fsl

xhci: optimize xhci bus resume time

We used to write the root port state changes in turn for every port,
sleeping 20ms after every port state change. Suspended usb2 ports need
two state changes, taking minimun 40ms per port.

Now instead poll the Port Link State Change (PLC) bit as
the state change to U0 will set this bit.
Suspended usb2 ports still need the extra 20ms delay, but we now change
all the port states at once so we only need to sleep 20ms once all together

Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>