linux-phytec-fsl

ARM: EXYNOS: Fix the incorrect hierarchy of spi controller bus clock

The sclk_spi clock is derived currently from the first level divider
(MMCx_RATIO) which is incorrect. The output of the first level clock
is divided by a second level divider (MMCx_PRE_RATIO), the output of
which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy
issues for the sclk_spi clock.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
[kgene.kim@samsung.com: changed the name of clk for consensus]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>