linux-phytec-fsl

clk_mux: Fix set_parent doing the wrong thing when INDEX_BIT && index >= 3

If CLK_MUX_INDEX_BIT is set, then each bit turns on / off a single parent,
so theoretically multiple parents could be enabled at the same time, but in
practice only one bit should ever be 1. So to select parent 0, set
the register (*) to 0x01, to select parent 1 set it 0x02, parent 2, 0x04,
parent 3, 0x08, etc.

But the current code does:

                if (mux->flags & CLK_MUX_INDEX_BIT)
                        index = (1 << ffs(index));

Which means that:

For an input index of 0, ffs returns 0, so we set the register
to 0x01, ok.

For an input index of 1, ffs returns 1, so we set the register
to 0x02, ok.

For an input index of 2, ffs returns 2, so we set the register
to 0x04, ok.

For an input index of 3, ffs returns 1, so we set the register
to 0x02, not good!

The code should simply be:

                if (mux->flags & CLK_MUX_INDEX_BIT)
                        index = 1 << index;

Which always does the right thing, this commit fixes this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>