Commits
Shengjiu Wang committed 6b111334302
MLK-12027: ARM: dts: fix the sample rate clock not accurate for spdif tx Clock of spdif tx is derived from clk_ipg and clk_osc, which is not the integer multiple size of sample rate, can't generate accurate clock for each sample rate. Use pll4 as the clk_spdif's parent, because the clk_spdif is the one of source clock of tx, use a proper frequency for pll4, then it can generate more accurate clock for sample rate (32k,48k,96k,192k). Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>