linux-phytec-fsl

MLK-11249-3 ARM: imx: improve i.mx6ul's low power idle setting

For low power idle with ARM power gated, per hardware requirement,
there must be no interrupt coming during the power down
process of ARM core, so RBC counter is enabled to hold interrupts.

However, the previous setting of RBC counter is 1, which is ~30us,
but the hardware design recommend a ~90us is required during ARM
core power down, so we update the RBC counter value to 4(~120us) here.

Previous delay loop to make sure RBC is actually enabled, 3us is
needed, but the loop value assume ARM is running @1GHz, but actually
ARM is running @24MHz now, so we need to update the loop value
according to ARM speed.

The ARM power up timing is based on IPG / 2048, IPG is 1.5MHz during
low power idle, so the total latency of cpuidle exit should be
updated accordingly.

Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit 4e1fd49da5e87c5cc23f053692e8d7648a4d4b21)