Commits
Qipan Li committed 818e91625aa
spi: sirf: correct TXFIFO empty interrupt status bit the old code uses wrong marco - SIRFSOC_SPI_FIFO_FULL is not for FIFO interrupt status, it is for FIFO status. here in the ISR, SIRFSOC_SPI_TXFIFO_EMPTY is the right bit for SPI TXFIFO interrupt status. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Mark Brown <broonie@linaro.org>