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![Masahiro Yamada](https://secure.gravatar.com/avatar/3cef3da146581babd52b939b53ec0609.jpg?s=96&d=mm)
Masahiro Yamada committed 955d809bdea
ARM: tegra: Remove redundant ARM_L1_CACHE_SHIFT_6 select These two are both ARMv7 SoCs. They need not explicitly select ARM_L1_CACHE_SHIFT_6 because it is enabled along with CPU_V7. Refer to commit a092f2b15399 ("ARM: 7291/1: cache: assume 64-byte L1 cachelines for ARMv7 CPUs"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Thierry Reding <treding@nvidia.com>