Commits
Quan Zhang committed ab5b05c3473
MLK-13206 dcp: mx6sl: add missing components in dts After MX6ULL DCP issue is fixed in commit 7a1cc1f, it introduces a new issue, MX6SL will meet issue as no dcp clock is defined when initializing: [ 3.061344] mxs-dcp 20fc000.dcp: can't identify DCP clk: -2 On mx6sl, dcp clock is always on, so the patch use dummy as dcp clock directly. Signed-off-by: Quan Zhang <spring.zhang@nxp.com>