linux-phytec-fsl

ASoC: rsnd: tidyup rsnd_ssi_master_clk_start() parameter

Renesas sound has SRC (= Sampling Rate Converter),
but, the HW implementation depends on its generation.
It was part of SRU on Gen1, and SCU on Gen2.
This SCU needs DMA transfer to use it.
Current rsnd driver is using it as DMA transfer buffer
(= no rate convert), and Gen1 is only supported at this point.

This patch cleanup it with focusing about SRC and Gen2 part.

ssi clock which is calculated from rsnd_ssi_master_clk_start()
should have flexibility since Renesas sound has
SRC (= Sampling Rate Converter).
But current implementation is using runtime->rate directly.
This patch tidyup rsnd_ssi_master_clk_start() parameter
as preparation of future SRC support

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@linaro.org>