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![Shengjiu Wang](https://secure.gravatar.com/avatar/836aa2d678d1acf93e4b518f470004bd.jpg?s=96&d=mm)
Shengjiu Wang committed bceb09b44ad
MLK-14679-1: ARM: clk: spdif clock rate is too high for asrc spdif clock is one of the asrc clock source, which is used for ideal ratio mode. when set to 98.304MHz, it cause the divider of asrc input clock and output clock exceed the maximum value, and asrc driver saturate the value to maximum value, which will cause the ASRC's performance very bad. So we need to set spdif clock to a proper rate. which make asrc divider not exceed maximum value, at least one of divider not exceed maximum value. The target is spdif clock rate / output(or input) sample rate less than 1024(which is maximum divider). Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>