linux-phytec-fsl

MLK-13455 ARM: imx: need to wait apll ready before operating MMDC on i.mx7ulp

When resume from VLPS mode on i.MX7ULP, APLL is NOT
valid yet, but MMDC clock is from APLL, so need to
wait for it valid before operating MMDC.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>