Commits
Paul Handrigan committed cadf2120ff7
ASoC: cs42l73: If Internal MCLK is >= 6.4MHz, then set SCLK to 64*Fs. Signed-off-by: Paul Handrigan <Paul.Handrigan@cirrus.com> Acked-by: Brian Austin <brian.austin@cirrus.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>