Commits
![Andre Przywara](https://secure.gravatar.com/avatar/3e4f28ff580d6746a4daff30b6997906.jpg?s=96&d=mm)
Andre Przywara committed d331328da6b
clk: sunxi: Improve divs_clk error handling and reporting We catch errors in the base clock registration, failure to ioremap and failures in the final of_clk_add_provider() call. Also we unmap the registers when we need to rollback. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>