Commits
Anson Huang committed dc8d5db1cde
MLK-13501 ARM: imx: correct i.mx7ulp clock tree setting
On i.MX7ULP, there are options to select SPLL or SPLL PFD
as SPLL output clock SPLL_SEL, so the SPLL option for
sys_sel mux should be from SPLL_SEL, NOT from SPLL directly.
Previous:
spll_pre_sel 1 1 24000000 0
spll_pre_div 1 1 24000000 0
spll 2 2 531648000 0
sys_sel 1 1 531648000 0
core_div 2 2 531648000 0
plat_div 1 1 531648000 0
spll_pfd3 0 0 979729408 0
spll_pfd2 0 0 979729408 0
spll_pfd1 0 0 979729408 0
spll_pfd0 1 1 503666526 0
spll_pfd_sel 0 0 503666526 0
spll_sel 0 0 503666526 0
After fixed:
spll_pre_sel 1 1 24000000 0
spll_pre_div 1 1 24000000 0
spll 1 1 531648000 0
spll_pfd3 0 0 979729408 0
spll_pfd2 0 0 979729408 0
spll_pfd1 0 0 979729408 0
spll_pfd0 2 2 503666526 0
spll_pfd_sel 1 1 503666526 0
spll_sel 1 1 503666526 0
sys_sel 1 1 503666526 0
core_div 1 1 503666526 0
plat_div 1 1 503666526 0
CORE_DIV clock will be enabled automatically when PLAT_DIV
is enabled, so we can skip it in clks_init_on.
Now that sys_sel clock tree is correct, no need to have SPLL_PFD0
in clks_init_on, as it will be enabled automatically because of
PLAT_DIV.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>