linux-phytec-fsl

MLK-13480-1 ARM: imx: improve composite clk parent index setting

The PCC clock bit field definition is as below:

000b - Clock is off.
001b - Clock option 1
010b - Clock option 2
011b - Clock option 3
100b - Clock option 4
101b - Clock option 5

So previous clock driver sets PCC clock parent to
start from index value 1 by setting CLK_MUX_INDEX_ONE
flag, however it has an issue of getting clock parent
when the register field value is 0, below is the clk
get parent code from clk driver:

if (val && (mux->flags & CLK_MUX_INDEX_BIT))
	val = ffs(val) - 1;

if (val && (mux->flags & CLK_MUX_INDEX_ONE))
	val--;

The val is 0, so the parent will be returned as first
clock parent in PCC register field which is 001b,
that will cause setting clk parent fail when the
reset value is 0 and we try to set clk parent to
option 1, as clk driver thinks current clk parent
is same as the new parent.

Fix this issue by adding dummy clock as option0, ths
clk gate is controlled by bit 30, so it would NOT impact
gating function.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>