Commits
Shengjiu Wang committed e65a014efe0
MLK-15042: ASoC: fsl_asrc: update supported format The ASRC support 24 bit input width, but for S20_3LE the input width is 20 bit, asrc will treat it as 24bit, which like a 24bit data shift 4 bit right, the result is the volume is lower than expected. ASRC can't shift the 20bit data left 4 bit internally, so remove the S20_3LE in supported list, add S24_3LE in supported list. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>