linux-phytec-ti

ARM: dts: omap44xx-clocks: Set IVA DPLL and its output clock rates

The IVA DPLL is not an essential DPLL for the functionality of a
bootloader and is usually not configured (e.g. older u-boots configure
it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer
than 2014.01 do not even have an option), and this results in incorrect
operating frequencies when trying to use a DSP or IVAHD, whose root
clocks are derived from this DPLL. Use the DT standard properties
"assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock
rate and the rates for its derivative clocks at boot time to properly
initialize/lock this DPLL. The DPLL will automatically transition
into a low-power stop mode when the associated output clocks are
not utilized or gated automatically.

The reset values of the dividers M4 & M5 (functional clocks for DSP and
IVAHD respectively) are identical to each other, but are different at
each OPP. The reset values also do not match a specific OPP. So, the
derived output clocks from the IVA DPLL have to be initialized as well
to avoid initializing these divider outputs to incorrect frequencies.

The clock rates are chosen based on the OPP100 values as defined in
the OMAP4430 ES2.x Public TRM vAP [1], section "3.6.3.8.7 DPLL_IVA
Preferred Settings". The DPLL locked frequency is 1862.4 MHz (value
for DPLL_IVA_X2_CLK), so the dpll_iva_ck clock rate used is half of
this value.

[1] www.ti.com/lit/pdf/swpu231

Signed-off-by: Suman Anna <s-anna@ti.com>