linux-phytec-ti

arm64: dts: ti: k3-j721e-main: Add C71x DSP node

The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.

NOTE:
The power-domains property is currently commented out until the
local resets integration is sorted out (not represented in SoC
data). Otherwise, the genpd integration tries to enable the DSP
(release from reset) even before the driver is probed.

Signed-off-by: Suman Anna <s-anna@ti.com>