linux-phytec-ti

ARM64: dts: marvell: armada-37xx: Enable memory-mapped GIC CPU interface

The Cortex-A53s that power the Armada-37xx SoCs are equipped with
a GIC CPU interface that gets enabled when coupled with a GICv3
interrupt controller, such as the GIC-500 on the this SoC.

Advertise the MMIO ranges provided by the CPUs, which enables
(among other things) GICv2 guests to run under a hypervisor such
as KVM.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>