linux-phytec-ti

phy: keystone: k2g: fix async abort during probe of phy serdes driver

SerDes is part of the peripheral device. With recent change to the
keystone SerDes driver, the phy provider may get initialized
before the peripheral device to which SerDes is part of. Depending
on the soc and peripheral in which the SerDes is included, and the
feature of the SerDes that is supported, such as 10gbe mcu firmware,
it may need the associated peripheral to be powered on and clocked
before initialization can be done successfully.

In the case of k2g pcie, an async abort is seen as below during
probe due to peripheral registers not accessible when register
writes happens if the peripheral clock is not enabled.

[    0.759672] ti,keystone-serdes 2320000.phy: init fw ks2_pcie_serdes.bin:
version 3.3.0.2c
[    0.768099] Unhandled fault: asynchronous external abort (0x211) at
0x00000000
[    0.775455] pgd = c0003000
[    0.778261] [00000000] *pgd=80000800004003, *pmd=00000000
[    0.783791] Internal error: : 211 [#1] PREEMPT ARM
[    0.788697] Modules linked in:
[    0.791862] CPU: 0 PID: 1 Comm: swapper Not tainted 4.4.19-02872-g3b233bc #13
[    0.799130] Hardware name: Keystone
[    0.802726] task: de050000 ti: de04e000 task.ti: de04e000
[    0.808255] PC is at kserdes_load_init_fw.constprop.3+0x194/0x1d0
[    0.814477] LR is at kserdes_load_init_fw.constprop.3+0x180/0x1d0
[    0.820697] pc : [<c02c6768>]    lr : [<c02c6754>]    psr: 60000013
[    0.820697] sp : de04fcb0  ip : 00000008  fp : de04fd24
[    0.832427] r10: de17f410  r9 : de0d3010  r8 : ffffffff
[    0.837771] r7 : f0888000  r6 : 00000000  r5 : de00bae0  r4 : de00b010
[    0.844426] r3 : f0888000  r2 : 00000000  r1 : 60000013  r0 : de1a4c80
[    0.851084] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment
kernel
[    0.858527] Control: 30c53c7d  Table: 00003000  DAC: fffffffd
[    0.864396] Process swapper (pid: 1, stack limit = 0xde04e208)

In the case of using mcu firmware to configure the 10gbe SerDes on k2hk
and k2e (a feature to be added soon), mcu firmware won't be able to
complete the SerDes configuration without the peripheral clock enabled
and will cause a system hang when peripheral registers are read/write
later.

This patch fixes this by adding support for clock enable through
runtime PM API calls during serdes driver probe.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>