Merge branch 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel into ti-linux-4.19.y
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-4.19.y
* 'connectivity-ti-linux-4.19.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel: (67 commits)
usb: cdns3: core: use dev_dbg() for debug prints
usb: cdns3: drd: use dev_dbg() for debug prints
arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0
arm64: dts: ti: k3-j721e-main.dtsi: Add USB to SERDES MUX
usb: cdns3: Support Type-C plug flip/lane swap
phy: cadence: Sierra: add phy_reset hook
phy: ti: j721e-wiz: Manage typec-gpio-dir
dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO
ti_config_fragments: connectivity.cfg: Enable PCIe related configs
ti_config_fragments: connectivity.cfg: Enable SERDES related configs
arm64: dts: ti: k3-j721e-common-proc-board: Configure all '3' PCIe instances in RC mode
arm64: dts: k3-j721e-main: Add PCIe device tree nodes
arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux
arm64: dts: ti: k3-j721e-main: Add dt for WIZ and SERDES
phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC
dt-bindings: phy: Document WIZ (SERDES wrapper) bindings
phy: cadence: Sierra: Set cmn_refclk/cmn_refclk1 frequency to 25MHz
phy: cadence: Sierra: Change MAX_LANES of Sierra to 16
phy: cadence: Sierra: Check for PLL lock during PHY power on
phy: cadence: Sierra: Get reset control "array" for each link
...
Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>
