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![Jan Kotas](https://secure.gravatar.com/avatar/1a638bf70339f4fbf57ac5adc324159f.jpg?s=96&d=mm)
Jan Kotas committed 6ded416d4ac
media: Fix Lane mapping in Cadence CSI2TX This patch fixes mapping of lanes in DPHY_CFG register of the controller. In the register, bit 0 means first data lane. In Linux we currently assume lane 0 is clock. Signed-off-by: Jan Kotas <jank@cadence.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>