Commits
Jyri Sarha committed 7ed36e96fd0
ASoC: tlv320aic31xx: Choose PLL p divider automatically This simplifies aic31xx_divs table. There is no more need for p_val or separate lines for 12 and 24 MHz mclks. Signed-off-by: Jyri Sarha <jsarha@ti.com> Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>