linux-phytec-ti

ARM: OMAP2+: use separate IOMMU pdata to fix DRA7 IPU1 boot

The IPU1 MMU has been using common IOMMU pdata quirks defined and
used by all IPU IOMMU devices on OMAP4 and beyond. Separate out the
pdata for IPU1 MMU with the additional .set_pwrdm_constraint ops
plugged in, so that the IPU1 power domain can be restricted to ON
state during the boot and active period of the IPU1 remote processor.
This eliminates the pre-conditions for the IPU1 boot issue as
described in commit abe8e5c766ef ("iommu/omap: fix boot issue on
remoteprocs with AMMU/Unicache").

NOTE:
1. The fix is currently applied only to IPU1 on DRA7xx SoC, as the
   other affected processors on OMAP4/OMAP5/DRA7 are in domains
   that are not entering RET. The fix can be easily scaled if these
   domains do hit RET in the future.
2. The issue may not be seen on current DRA7 platforms if any of the
   DSP remote processors are booted and using one of the GPTimers
   5, 6, 7 or 8. This is due to the errata fix for i874 implemented
   in commit 1cbabcb9807e ("ARM: DRA7: clockdomain: Implement timer
   workaround for errata i874") which keeps the IPU1 power domain
   from entering RET when the timers are active.

Signed-off-by: Suman Anna <s-anna@ti.com>