linux-phytec-ti

mtd: spi-nor: cadence-quadspi: add a delay in write sequence

As per 66AK2G02 TRM SPRUHY8 section 11.14.5.3 Indirect Access Controller
programming sequence, a delay equal to couple QSPI master clock(~5ns) is
required after setting CQSPI_REG_INDIRECTWR_START bit and writing data
to the flash. Add a new compatible to handle the couple of cycles of
delay required in the indirect write sequence, since this delay is
specific to TI K2G SoC.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>