linux-phytec-ti

phy: ti: j721e-wiz: Implement DisplayPort mode to the wiz driver

For DisplayPort use we need to set WIZ_CONFIG_LANECTL register's
P_STANDARD_MODE bits to "mode 3". In the DisplayPort use also the
P_ENABLE bits of the same register are set to P_ENABLE instead of
P_ENABLE_FORCE, so that the DisplayPort driver can enable and disable
the lane as needed. The DisplayPort mode is selected according to
lane<n>-mode -property. All other values of lane<n>-mode -property but
PHY_TYPE_DP will set P_STANDARD_MODE bits to 0 and P_ENABLE bits to
force enable.

History

This patch replaces the earlier hard coded hack for DisplayPort use
and uses new "port-use" dts property to select use mode for each lane
separately.

It appears the only mandatory part of the earlier hack was setting a
different mode for all the DP lanes. Also the LANECTL P0_FORCE_ENABLE
for lane 0 is changed to P0_ENABLE. The both settings appear to work,
but using P0_FORCE_ENABLE may prevent lane reset from the controller
to take effect.

With this patch the DisplayPort still works, but all the register do
not have the same values as before.

Here is the diff between wiz setting before and after this patch:

Register                   | Earlier    | Now        | Functional change
WIZ_SERDES_TOP_CTRL 0x408  | 0x30000000 | 0xb8000000 | Ext ref clk only [1]
WIZ_SERDES_RST      0x40c  | 0x39000000 | 0x31000000 | Ext ref clk only [2]
WIZ_LANECTL(0)      0x480  | 0x70000000 | 0x80000000 | Force enable, align.. [3]
WIZ_LANECTL(1)      0x4c0  | 0x80000000 | 0x80000000 |
WIZ_LANECTL(2)      0x500  | 0x80000000 | 0x80000000 |
WIZ_LANECTL(3)      0x540  | 0x80000000 | 0x80000000 |
WIZ_LANEDIV(0)      0x484  | 0x00010001 | 0x00000000 | The divider is unused
WIZ_LANEDIV(1)      0x4c4  | 0x00010001 | 0x00000000 | The divider is unused
WIZ_LANEDIV(2)      0x504  | 0x00010001 | 0x00000000 | The divider is unused
WIZ_LANEDIV(3)      0x544  | 0x00010001 | 0x00000000 | The divider is unused

The above is before Wiz is taken out of reset (0x40c bit 31).

[1] Bits 31-30 sets external PMA common differential reference clock
    mode. Setting 10 is for under 100Mhz rates (the old 00 is for greater
    than 100MHz rates). J721E evm uses internal reference clock.

[2] Bit 27 disables termination for the external PMA common differential
    reference clock. J721E evm uses internal reference clock.

[3] Bit 29 is auto align to 8B10B comma characters and 28 is auto
    sequence the RAW interface according to the configuration
    settings, neither should affect DisplayPort behavior. Bit 31 is
    normal enable and 30 is force enable.

Signed-off-by: Jyri Sarha <jsarha@ti.com>