linux-phytec-ti

spi-nor: cadence-quadspi: Add support for PHY configuration

Cadence Octal SPI controller IP has integrated PHY to enable high speed
Octal SDR/DDR mode data transfers between controller and flash at lower
functional clock.
This patch adds support for PHY calibration and operation in Octal SDR
mode. Using PHY mode, enforces a restriction that transactions need to
be 4 byte aligned but on arm64, memcpy_fromio() does either 8 byte
accesses or single byte accesses, therefore all reads needs to be
aligned to 8 byte boundary. So, introduce a intermediate bounce buffer
mechanism wherein data is first read from flash to bounce buffer
honoring the alignment constraints. Then copy the actual requested
range of data from bounce buffer to final destination buffer.

Reviewed-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>