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Florian Fainelli
a4c0201e230
Florian Fainelli committed af2418be63b
MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value

Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift
value of 4) instead of the currently configured 32 bytes L1-cache line
size.

Reported-by: Daniel Gonzalez <dgcbueu@gmail.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>