Commits
Anson Huang committed ba7f4f557eb
clk: imx: correct AV PLL rate formula The audio/video PLL's rate calculation is as below in RM: Fref * (DIV_SELECT + NUM / DENOM), in origin clk-pllv3's code, below code is used: (parent_rate * div) + ((parent_rate / mfd) * mfn as it does NOT consider the float data using div, so below formula should be used as a decent method: (parent_rate * div) + ((parent_rate * mfn) / mfd) and we also need to consider parent_rate * mfd may overflow a 32 bit value, 64 bit value should be used. After updating this formula, the dram PLL's rate is 1066MHz, which is correct, while the old formula gets 1056MHz. [Aisheng: fix clk_pllv3_av_round_rate too] Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>