Merge tag 'meson-clk-5.2' of https://github.com/BayLibre/clk-meson into clk-meson
Pull Amlogic Meson clk driver updates from Neil Armstrong:
- Adds VPU and Video Decoder clocks on Meson8b
- Finally remove the wrong ABP Meson8b clock id
- Adds Video Decoder, PCIe PLL & CPU Clocks on G12A
- Re-expose SAR_ADC_SEL and CTS_OSCIN on G12A AO clock controller
- Un-expose some AXG-Audio input clocks IDs
* tag 'meson-clk-5.2' of https://github.com/BayLibre/clk-meson:
clk: meson: meson8b: add the video decoder clock trees
clk: meson: meson8b: add the VPU clock trees
clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2
clk: meson: meson8b: use a separate clock table for Meson8m2
clk: meson-g12a: add video decoder clocks
clk: meson-g12a: add PCIE PLL clocks
clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL
clk: meson: g12a: add cpu clocks
dt-bindings: clock: meson8b: export the video decoder clocks
dt-bindings: clock: meson8b: export the VPU clock
dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN
dt-bindings: clock: meson8b: drop the "ABP" clock definition
dt-bindings: clk: g12a-clkc: add VDEC clock IDs
dt-bindings: clock: axg-audio: unexpose controller inputs
dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID
clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id
clk: meson-g12a: add cpu clock bindings
